In general, most of memory devices such as a random access memory (RAM) employ one port at which lots of input/output (I/O) pin sets are located. That is, a memory device has only one port for data exchange with a chipset. However, recently, it is getting ambiguous to classify functions of the chipset and those of the memory device, and the integration of the chipset and the memory device is considered. In view of this tendency, there is required a multi-port memory device capable of directly exchanging data with its peripheral devices such as a graphic device, a CPU and so on. In order to implement the multi-port memory device, any one of many ports should be accessible to all memory cells.
An interface originally means a border, a contact surface or an area shared by two components, i.e., two functional units. In a system or device, the interface means the interconnection between devices having different functions. On the other hand, for the data transmission, it includes physical connection conditions between two systems or devices, mechanical conditions such as a physical surface, an interval of a connection component or a sub-system and so on, electric conditions such as a matching signal level, impedance, a power level, etc., and specifications for a signal format and a circuit type relating to the interconnection between two devices or systems.
Meanwhile, although there are lots of interfaces such as an I/O interface, a man-machine interface, a system-call interface, a communication protocol and so on, the I/O interface will be only considered hereinafter.
The I/O interface is an electrical and mechanical treating method so as to exactly transfer transmitting/receiving information to other parts when performing the communication by connecting different functional units with signal lines. The signal lines are unified and called a bus. There are a data bus, a control bus, a ground bus and so on and the number of signal lines of the bus is varied according to a feature of the interface.
In case of a parallel I/O interface, while the data transmission efficiency (speed) is superior since it is possible to transmit several bit data at the same time through several signal lines, a transmission cost increases as a data transmission distance becomes longer when the number of signal lines is great. Therefore, the parallel I/O interface is used at a short data transmission distance requiring a high speed.
In case of a serial I/O interface, the data transmission is performed through one signal line. Therefore, although its data transmission speed is lower than that of the parallel I/O interface, it has a simpler hardware structure and a control scheme than the parallel I/O interface. However, it is not true that the serial transmission scheme is always slower than the parallel transmission scheme.
In a computer, there are lots of devices whose bit transmission is executed in parallel. The RAM generally used as an auxiliary memory device also employs the parallel I/O interface. Namely, the RAM exchanges data in parallel with external devices through a plurality of I/O pins (DQ).
In the meantime, as described above, an effort to change the conventional parallel I/O interface to the serial I/O interface continues so as to compensate the disadvantages of the parallel I/O interface. The interface in the RAM is also required to be changed to the serial I/O interface with regard to the compatibility with other serial I/O interface devices. Furthermore, in case of the above multi-port memory device, since it has a plurality of ports, and the numbers of pads and pins increases in proportion to the number of ports when it uses the parallel I/O interface, it is inevitable that there follows a difficulty in packaging. Therefore, it is advantageous to adopt the serial I/O interface in the multi-port memory device.
Referring to FIG. 1, there is shown a floor plan of a multi-port memory device having 8 banks according to a conventional DRAM structure.
In FIG. 1, the multi-port memory device includes a core area 10 divided into an upper and a lower portion, a global data bus GIO and a plurality of ports 14, which are arranged at its central area. A control block 12 is also located at the central area between the upper portion and the lower portion of the core area 10. At each of the upper and the lower portions of the core area 10, there are arranged 4 banks, e.g., bank0, bank2, bank4 and bank6 at the upper portion, and bank1, bank3, bank5 and bank7 at the lower portion in a row direction.
In case of adopting this architecture, since there exists a blank area between banks, wherein the blank area due to wires (not shown) between the upper/lower banks and the global data bus GIO and the plurality of ports, the layout efficiency is deteriorated.
Referring to FIG. 2, there is illustrated a floor plan of a multi-port memory device having ports arranged at one side of a core area.
In FIG. 2, the multi-port memory device includes 8 banks, bank0 to bank7, arranged in a row direction without dividing a core area 20, one global data bus GIO and a multiplicity of ports 24 arranged at a lower part (or upper part) of the core area 20. A control block 22 is located at a center of the lower part of the core area 20.
While there is an effect that the blank area is reduced when adopting the architecture shown in FIG. 2, a die shape is vertically long and the ports and global data bus GIO lean to one side. As a result, the easiness of packaging and the expandability such as the integration capability and the number of banks are deteriorated.
FIG. 3 is a floor plan of a multi-port memory device having ports arranged at both sides of a core area.
In FIG. 3, although a core area 30 of the multi-port memory device is not divided, the arrangement of banks, e.g., bank0 to bank7, is similar to that in FIG. 1 and a multiplicity of ports 34 is arranged in an upper and a lower part of the core area 30. A global data bus GIO is located at three sides along with edges of the core area 30 and a control block 32 is located at one side of the core area 30.
In case of adopting this architecture, although it is possible to overcome the problems that the architectures in FIGS. 1 and 2 have, the line length of the global data bus GIO becomes longer, resulting in the increase of the loading of the global data bus GIO seen by the banks, bank0 to bank7, and the ports 34.
The problems described above are getting serious as the number of banks and that of signal lines of the global data bus GIO are greater, the number of signal lines closely relating to a bandwidth.